Consider the circuit arrangement shown in figure for studying input and output characteristics of $n-p-n$ transistor in CE configuration. Select the values of $R_B$ and $R_C$ for a transistor whose $V_{\mathrm{BE}}=0.7 \mathrm{~V}$, so that the transistor is operating at point $Q$ as shown in the characteristics (see figure).
Given that the input impedance of the transistor is very small and $V_{C C}=V_{B B}=16 \mathrm{~V}$, also find the voltage gain and power gain of circuit making appropriate assumptions.
$$\begin{aligned} &\begin{aligned} \text{Given,}\quad V_{B E} & =0.7 \mathrm{~V}, V_{\mathrm{CC}}=V_{\mathrm{BB}}=16 \mathrm{~V} \\ V_{\mathrm{CE}} & =8 \mathrm{~V} \text { (from graph) }\\ I_C & =4 \mathrm{~mA}=4 \times 10^{-3} \mathrm{~A} \\ I_B & =30 \propto \mathrm{~A}=30 \times 10^{-6} \mathrm{~A} \end{aligned}\\ \end{aligned}$$
$$\begin{aligned} &\text { For the output characteristic at } \theta \text {, }\\ &\begin{aligned} V_{C C} & =I_C R_C+V_{C E} \\ R_C & =\frac{V_{C C}-V_{C E}}{I_C}=\frac{16-8}{4 \times 10^{-3}}=\frac{8 \times 1000}{4}=2 \mathrm{k} \Omega \end{aligned} \end{aligned}$$
$$\begin{aligned} &\text { Using the relation, }\\ &\begin{aligned} V_{\mathrm{BB}} & =I_B R_B+V_{\mathrm{BE}} \\ R_B & =\frac{V_{\mathrm{BB}}-V_{\mathrm{BE}}}{I_B}=\frac{16-0.7}{30 \times 10^{-6}} \\ & =510 \times 10^3 \Omega=510 \mathrm{k} \Omega \\ \beta & =\frac{I_C}{I_B}=\frac{4 \times 10^{-3}}{30 \times 10^{-6}}=133 \\ \text { Voltage gain } & =\beta \frac{R_C}{R_B}=\frac{133 \times 2 \times 10^3}{510 \times 10^3}=0.52 \\ \text { Power gain } & =\beta \times \text { Voltage gain }=133 \times 0.52=69 \end{aligned} \end{aligned}$$
Assuming the ideal diode, draw the output waveform for the circuit given in fig. (a), explain the waveform.
When the input voltage is equal to or less than 5 V , diode will be revers biased. It will offer high resistance in comparison to resistance (R) in series. Now, diode appears in open circuit. The input waveform is then passed to the output terminals. The result with sin wave input is to dip off all positive going portion above 5 V.
If input voltage is more than +5 V , diode will be conducting as if forward biased offering low resistance in comparison to $R$. But there will be no voltage in output beyond 5 V as the voltage beyond +5 V will appear across $R$.
When input voltage is negative, there will be opposition to 5 V battery in $p-n$ junction input voltage becomes more than $-$5 V , the diode will be reverse biased. It will offer high resistance in comparison to resistance $R$ in series. Now junction diode appears in open circuit. The input wave form is then passed on to the output terminals.
The output waveform is shown here in the fig. (b)
Suppose a $n$-type wafer is created by doping Si crystal having $5 \times 10^{28}$ atoms $/ \mathrm{m}^3$ with 1 ppm concentration of As. On the surface 200 ppm boron is added to create ' $p$ ' region in this wafer. Considering $n_i=1.5 \times 10^{16} \mathrm{~m}^{-3}$, (i) Calculate the densities of the charge carriers in the $n$ and $p$ regions. (ii) Comment which charge carriers would contribute largely for the reverse saturation current when diode is reverse biased.
When As is implanted in Si crystal, $n$ - type wafer is created. The number of majority carriers electrons due to doping of As is
$$\begin{aligned} n_e & =N_D=\frac{1}{10^6} \times 5 \times 10^{28} \\ & =5 \times 10^{22} / \mathrm{m}^3 \end{aligned}$$
Number of minority carriers (holes) in $n$-type wafer is
$$\begin{aligned} n_h & =\frac{n_i^2}{n_e}=\frac{\left(1.5 \times 10^{16}\right)^2}{5 \times 10^{22}} \\ & =0.45 \times 10^{10} / \mathrm{m}^3 \end{aligned}$$
When $B$ is implanted in Si crystal, p-type wafer is created with number of holes,
$$n_h=N_A=\frac{200}{10^6} \times\left(5 \times 10^{28}\right)=1 \times 10^{25} / \mathrm{m}^3$$
Minority carriers (electrons) created in p-type wafer is
$$\begin{aligned} n_e & =\frac{n_i^2}{n_h}=\frac{\left(1.5 \times 10^{16}\right)^2}{1 \times 10^{25}} \\ & =2.25 \times 10^{27} / \mathrm{m}^3 \end{aligned}$$
When $p-n$ junction is reverse biased, the minority carrier holes of $n$-region wafer ( $n_h=0.45 \times 10^{10} / \mathrm{m}^3$ ) would contribute more to the reverse saturation current than minority carrier electrons $\left(n_e=2.25 \times 10^7 / \mathrm{m}^3\right)$ of pregion wafer.
An X-OR gate has following truth table.
It is represented by following logic relation $Y=\bar{A} \cdot B+A \cdot \bar{B}$
Build this gate using AND, OR and NOT gates.
Given, the logic relation for the given truth table is
$$\begin{aligned} Y & =\bar{A} \cdot B+A \cdot \bar{B}=Y_1+Y_2 \\ \text{when}\quad Y_1 & =A \cdot B \text { and } Y_2=A \cdot \bar{B} \end{aligned}$$
$Y_1$ can be obtained as output of AND gate I for which one Input is of $A$ through NOT gate and another input is of $B$. $Y_2$ can be obtained as output of AND gate II for which one input is of $A$ and other input is of $B$ through NOT gate.
Now $Y_2$ can be obtained as output from OR gate, where, $Y_1$ and $Y_2$ are input of OR gate. Thus, the given table can be obtained from the logic circuit given below
Consider a box with three terminals on top of it as shown in figure.
Three components namely, two germanium diodes and one resistor are connected across these three terminals in some arrangement. A student performs an experiment in which any two of these three terminals are connected in the circuit shown in figure. The student obtains graphs of current-voltage characteristics for unknown combination of components between the two terminals connected in the circuit. The graphs are
(i) when $A$ is positive and $B$ is negative
(ii) when A is negative and B is positive
(iii) when B is negative and C is positive
(iv) when B is positive and C is negative
(v) when A is positive and C is negative
(vi) when A is negative and C is positive
From these graphs of current - voltage characteristic shown in fig. (c) to (h) determine the arrangement of components between $A, B$, and $C$.
(a) In V-I graph of condition (i), a reverse characteristics is shown in fig. (c). Here $A$ is connected to $n$ - side of $p-n$ junction $I$ and $B$ is connected to $p$-side of $p-n$ junction I with a resistance in series.
(b) In V-I graph of condition (ii), a forward characteristics is shown in fig. (d), where 0.7 V is the knee voltage of $p-n$ junction I $1 /$ slope $=(1 / 1000) \Omega$. It means $A$ is connected to $n$-side of $p-n$ junction $I$ and $B$ is connected to $p$-side of $p-n$ junction $I$ and resistance $R$ is in series of $p-n$ junction $I$ between $A$ and $B$.
(c) In V-I graph of condition (iii), a forward characteristics is shown in figure (e), where 0.7 V is the knee voltage. In this case $p$-side of $p-n$ junction II is connected to $C$ and $n$-side of $p-n$ junction II to $B$.
(d) In V-I graphs of conditions (iv), (v), (vi) also concludes the above connection of $p-n$ junctions I and II along with a resistance $R$.
Thus, the arrangement of $p-n I, p-n I I$ and resistance $R$ between $A, B$ and $C$ will be as shown in the figure